Using ... | Digital System Test And Testable Design:

A distinguishing feature is the extensive use of the Verilog Programming Language Interface (PLI) . This allows for a mixed hardware/software environment where users can develop "virtual testers" to evaluate complex test strategies.

Logic BIST basics, test pattern generation, and output response analysis. Digital System Test and Testable Design: Using ...

Gate-level faults, fault collapsing, and structural modeling in Verilog. A distinguishing feature is the extensive use of

Verilog is used to describe the internal architectures of Built-In Self-Test (BIST) and Design for Testability (DFT) . This helps engineers evaluate hardware overhead and timing feasibility, which is critical for System-on-Chip (SoC) designs. test pattern generation

Memory fault models, MBIST (Memory BIST) methods, and functional procedures.